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Ship it! This looks better. It would be even better still if we could get rid of that last ISA_HAS_DELAY_SLOT, but that might be hard to do. In O3 I made fetch walk past skipped instructions and I think I might have even still had an ISA_HAS_DELAY_SLOT in there. - Gabe On 2011-02-03 09:59:35, Korey Sewell wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/449/ > ----------------------------------------------------------- > > (Updated 2011-02-03 09:59:35) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > inorder: pcstate and delay slots bug > not taken delay slots were not being advanced correctly to pc+8, so for those > ISAs > we 'advance()' the pcstate one more time for the desired effect > > > Diffs > ----- > > src/cpu/inorder/resources/bpred_unit.cc 31a04e5ac4be > src/cpu/inorder/resources/branch_predictor.cc 31a04e5ac4be > src/cpu/inorder/resources/fetch_seq_unit.cc 31a04e5ac4be > > Diff: http://reviews.m5sim.org/r/449/diff > > > Testing > ------- > > > Thanks, > > Korey > >
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