Hi All,
Any thoughts on that matter ? Because not having these instructions
identified as control instructions causes the branch predictor to not
predict them, increasing the number of branch mispredictions.
It seems that some load instructions have also this problem.
Thanks,
Nathanaël
Le 23/08/2012 01:19, Nathanaël Prémillieu a écrit :
Hi All,
I happen to see that for data instructions in the ARM ISA (for example
an ADD) that have the PC as their destination register are not set as
control instructions (i.e. the flag IsControl is not set).
I was wondering whether it is a bug or it has some logic.
Thanks,
Nathanaël
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