Hi Nathanaël, The use of data instructions as branches is deprecated so we chose not to mark them as branches and I'd hope you're not seeing too much use of them. If you care the isBranch kwarg can be passed to the various data instructions in src/arch/arm/isa/insts/data.isa like it is for the mov instruction to mark these as branches. As for the loads, I believe these are correct, although it's always possible we missed some. In gem5 the load operations are turned into to uops one that does the memory load and a second that is the control instruction. Is this not what you're observing?
Thasks, Ali On Aug 28, 2012, at 4:35 AM, Nathanaël Prémillieu wrote: > Hi All, > > Any thoughts on that matter ? Because not having these instructions > identified as control instructions causes the branch predictor to not predict > them, increasing the number of branch mispredictions. > It seems that some load instructions have also this problem. > > Thanks, > > Nathanaël > > Le 23/08/2012 01:19, Nathanaël Prémillieu a écrit : >> Hi All, >> >> I happen to see that for data instructions in the ARM ISA (for example >> an ADD) that have the PC as their destination register are not set as >> control instructions (i.e. the flag IsControl is not set). >> I was wondering whether it is a bug or it has some logic. >> >> Thanks, >> >> Nathanaël >> _______________________________________________ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
