Hi Nathanaël,
Sent from my ARM powered mobile device
On Aug 28, 2012, at 11:34 AM, Nathanaël Prémillieu <nprem...@irisa.fr
<mailto:nprem...@irisa.fr>> wrote:
Hi Ali, Thank for your response. I was thinking that data
instructions as branch was a specificity of ARMv7. In The ARM
Architecture Reference Manual, p. 170, it is stated that: "In ARMv7,
a processor in ARM state can also enter Thumb state (and change to
executing Thumb instructions) by executing an ADC, ADD, AND, ASR,
BIC, EOR, LSL, LSR, MOV, MVN, ORR, ROR, RRX, RSB, RSC, SBC, or SUB
instruction that has the PC as destination register and does not set
the condition flags." I don't currently know if it happens a lot and
if it is responsible for a significative part of the detected
mispredictions. I will send some update when I will have numbers.
Thanks for looking into it and please let us know. Looking at the reference
manual it appears as though I wasnt quite correct. See table D4 in version 406B
of the manual or I5 in version 406C. It seems like we're missing a few that
aren't deprecated.
I have started to modify the src/arch/arm/isa/insts/data.isa file and
it seems to work. For the load instructions,
LOAD_REG_AN_PN_SN_UN_WN_SZ4, LOAD_IMM_AN_PN_SN_UN_WN_SZ4,
LOAD_REG_AY_PN_SN_UN_WN_SZ4 and LOAD_IMM_AY_PN_SN_UN_WN_SZ4 are not
split in two and the control flag is not set when it is necessary.
Hrm. This is probably a bug.
Thanks,
Ali
Thanks, Nathanaël Le 28/08/2012 15:32, Ali Saidi a écrit :
Hi Nathanaël, The use of data instructions as branches is deprecated
so we chose not to mark them as branches and I'd hope you're not
seeing too much use of them. If you care the isBranch kwarg can be
passed to the various data instructions in
src/arch/arm/isa/insts/data.isa like it is for the mov instruction
to mark these as branches. As for the loads, I believe these are
correct, although it's always possible we missed some. In gem5 the
load operations are turned into to uops one that does the memory
load and a second that is the control instruction. Is this not what
you're observing? Thasks, Ali On Aug 28, 2012, at 4:35 AM, Nathanaël
Prémillieu wrote:
Hi All, Any thoughts on that matter ? Because not having these
instructions identified as control instructions causes the branch
predictor to not predict them, increasing the number of branch
mispredictions. It seems that some load instructions have also this
problem. Thanks, Nathanaël Le 23/08/2012 01:19, Nathanaël
Prémillieu a écrit :
Hi All, I happen to see that for data instructions in the ARM ISA
(for example an ADD) that have the PC as their destination
register are not set as control instructions (i.e. the flag
IsControl is not set). I was wondering whether it is a bug or it
has some logic. Thanks, Nathanaël
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