On Fri, January 25, 2013 6:54 pm, Chen Tian wrote: > Hi, > > Is there any document on O3 implementation? I cannot get my head around > the > logic where in each cpu tick, fetch stage is first ticked then decode , > rename, iew and finally commit. I always thought it should be in reverse > order because an earlier stage in the same cycle does not know what > resource will be available if processed first. Can somebody please explain > to me? Thanks. >
I am slightly astounded by your comment that the stages should be ticked in reverse. We trying to implement something that happens in parallel in actual hardware. So, ideally all orders in which the the different stages can be processed should result in the same final state. There might be things in the code that are specific to gem5's implementation of an O3 cpu and hence require stages to processed in certain order. The documentation on this page is probably the best you can find -- http://gem5.org/O3CPU -- Nilay _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
