On Sat, January 26, 2013 12:01 pm, Chen Tian wrote: > Thanks everyone for your reply. I have a better understanding but still > have questions. > > Let's consider a time buffer B between two consecutive pipeline stages X > and Y. When computing Y's output at cycle t, do we need the signal passed > from X at t or t-1 (i.e., the struct in B with index t or t-1)? > Similarly, > when computing X's output at cycle t, do we need to look at the status of > Y > at cycle t or t-1 (e.g., whether some hw resource is available for this > cycle)? If both answers are t-1, which means the output of any stage only > depends on some other stages' output at previous cycle, then I can > understand why time buffer can get ride of the dependencies. However, if a > stage requires a result from another stage at the same cycle, I cannot see > how this works. Maybe hardware never does that -- as it is not actually > "parallel" between stages. I am not an expert on hardware and simulator. I > really appreciate it if someone help me understand this. >
Can you explain to me what you mean by a pipeline and a stage in a pipeline? Further, you need to explain what you mean by hardware not being actually parallel between stages. In my opinion, one does not need to be an expert (as I define it for myself) to understand a pipelined cpu or a cpu simulator. These topics are usually part of undergraduate curriculum for computer engineering / science. You should read some under-graduate textbooks on designing digital circuits and computer architecture. It seems that would be more helpful rather than trying to understand how gem5 implements an out-of-order cpu. -- Nilay _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
