Hi Chen, I wouldnt worry about the level of complexity of your questions. They are fine. If you want to understand the design complexity of any given component of the simulator and show that you have spent at least some time trying to understand the question on your own, then that's what the mailing list is for. My only advice is that when you ask a open-ended question like you asked, make sure you include details of what you've done prior to look into the question... "I dont understand the O3 CPU tick logic. I've looked at simplescalar and the InOrder models, and these tick backward to forward whereas O3 ticks forward to backward. How can O3 guarantee data is flowed through stages..etc. etc."
Mitch had some good explanation of the timebuffers... Can we get that on the Wiki Mitch? The only thing I would asterisk from Mitch's statement is: "The reason gem5 does this is it lets us fake longer/more detailed pipestages easily." - For the Simple model, all pipeline stages are merged into one :) - The InOrder model instantiates each stage rather then create a long timebuffer queue between each stage. Quick Points on Chen's original question: - If two stage A neesd data from stage B on the same cycle then: ---> In gem5, you can write to time 0 in the timebuffer which represents the current cycle. Timebuffers are actually represented as "wires" and setup during construction time. ---> The "correct" way to solve this harkens back to Andreas' answers and that is to have the ability to have "delta" cycles within a tick. It's more of a "SystemC" simulation methodology and I bring it up just in for completeness sake. ---> Are Stage A and stage B really independent pipelined stages? For instance, why would Fetch need data from Decode on the same cycle? The out-of-order engine needs to talk to each other, which is part of why IEW (issue-execute-write) is all in one stage. Without true "delta" cycles, there is some dependency I agree, but timebuffers and pipeline construction solve most issues. -- - Korey
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