I’m trying to configure a multi-port shared L1 cache among 4 cpus. The
structure should look like this:
cpu0 cpu1 cpu2 cpu3
| | | |
| | | | slave port of shared l1 bus
————————————————
shared l1 bus
————————————————
| |
| |master port of shared l1 bus
shared l1C0 shared l1C1
I modified the python file to achieve this (assign each shared l1C with a
different address range). However, the simulation ended with a message:
panic: system.tol1icachebus.master[0] was not expecting a timing snoop request
It seems that the snooping protocol do not approve two master ports.
Is there any convenient way to implement my structure?
Best，
Kunta Zhang
[email protected]
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