Hi Andreas,
I changed the configuration file to use CoherentBus now. But another
error happened as follows:
gem5.opt: build/ALPHA/mem/coherent_bus.cc:315: void
CoherentBus::recvTimingSnoopReq(PacketPtr, PortID): Assertion `master_port_id
== findPort(pkt->getAddr())' failed.
In CacheConfig.py I added the following lines to configure the desired
structure:
if options.sharedl1icache or options.sharedl1icachewithl0:
system.sharedl1icache0 = icache_class(#clock = options.clock,
size = options.l1i_size,
assoc = options.l1i_assoc,
addr_ranges = AddrRange(0, 268435455))
system.sharedl1icache1 = icache_class(#clock = options.clock,
size = options.l1i_size,
assoc = options.l1i_assoc,
addr_ranges =
AddrRange(268435456,536870911))
system.tol1icachebus = CoherentBus(clk_domain = system.cpu_clk_domain,
width = 32) #clock =
options.clock, width = 32)
system.sharedl1icache0.cpu_side = system.tol1icachebus.master
system.sharedl1icache1.cpu_side = system.tol1icachebus.master
if options.l2cache != True:
print "sharedL1Icache requires a l2 cache, please configue it"
sys.exit(1)
system.sharedl1icache0.mem_side = system.tol2bus.slave
system.sharedl1icache1.mem_side = system.tol2bus.slave
I turned the debug flags on and found the assertion failing was caused
by a snooping message for address 0x13081c0( in addrRange(0, 256MB)) on master
port[1] of tol1icachebus. However, the master port[1] of tol1cachebus was
configured to connected with sharedl1icache1 which has address range(256MB to
512MB). Therefore, the assertion failed.
Thanks for your reply!
在 2014年1月20日，下午4:31，Andreas Hansson <[email protected]> 写道：
> Hi Kunta,
>
> Did you manage to resolve this? Could you verify that you are using a
> CoherentBus?
>
> From your diagram I do not see why it would not work, but there are some
> hidden assumptions around the port interactions between the o3 cpu/caches/bus
> that you might have stumbled upon.
>
> If you’re still stuck on this I’d suggest running with the Bus and Cache
> debug flags to get some more insight.
>
> Andreas
>
> From: kunta Zhang <[email protected]>
> Reply-To: gem5 users mailing list <[email protected]>
> Date: Saturday, 21 December 2013 03:57
> To: gem5 users mailing list <[email protected]>
> Subject: [gem5-users] multi-port shared cache
>
> I’m trying to configure a multi-port shared L1 cache among 4 cpus. The
> structure should look like this:
>
> cpu0 cpu1
> cpu2 cpu3
> | |
> |
> |
> | |
> |
> | slave port of shared l1 bus
> ————————————————
> shared l1 bus
> ————————————————
> |
> |
> |
> |master port of shared l1 bus
> shared l1C0 shared l1C1
>
> I modified the python file to achieve this (assign each shared l1C with a
> different address range). However, the simulation ended with a message:
> panic: system.tol1icachebus.master[0] was not expecting a timing snoop request
>
> It seems that the snooping protocol do not approve two master ports.
>
> Is there any convenient way to implement my structure?
>
> Best，
> Kunta Zhang
> [email protected]
>
>
>
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