Re: [gem5-users] multi-port shared cache

kunta Zhang Thu, 23 Jan 2014 01:06:38 -0800

Hi Andreas,

Thank a lot for the patch!

The patch works fine.

That's very kind of you to remind me the AddrRange type although I've already refereed to it and succeeded to create interleaved address ranges.

2014年1月23日下午04:31，Andreas Hansson <[email protected]> 写道：

Hi Kunta,

The use of forward_snoops as you describe is not safe I’m afraid, as the CPU in certain situations relies on seeing the snoop. I have posted a patch that should fix your problem: http://reviews.gem5.org/r/2152/

The underlying issue was that you, for the first time, put re-converging caches in parallel. Without this patch, the caches forward the snoops irrespective of whether they belong to their address range or not. Let me know if the patch works.

Just as a side note, you know that you can also create interleaved address ranges? Have a look at the AddrRange type in params.py if you want to be a bit more creative with how to stripe across the parallel caches. I’m not sure how relevant this is to what you do, but it might prove useful.

Andreas

From: kunta Zhang <[email protected]>
Reply-To: gem5 users mailing list <[email protected]>
Date: Thursday, 23 January 2014 02:28
To: gem5 users mailing list <[email protected]>
Subject: Re: [gem5-users] multi-port shared cache

I think I've solved the problem by configure the sharedl1cache0/1 with "forward_snoops = false" since they are instruction caches. Therefore the snooping message to CoherentBus will be blocked.

2014年1月20日下午10:02，kunta Zhang <[email protected]> 写道：

Hi Andreas,

I changed the configuration file to use CoherentBus now. But another error happened as follows:
gem5.opt: build/ALPHA/mem/coherent_bus.cc:315: void CoherentBus::recvTimingSnoopReq(PacketPtr, PortID): Assertion `master_port_id == findPort(pkt->getAddr())' failed.
In CacheConfig.py I added the following lines to configure the desired structure:
if options.sharedl1icache or options.sharedl1icachewithl0:
system.sharedl1icache0 = icache_class(#clock = options.clock,
size = options.l1i_size,
assoc = options.l1i_assoc,
addr_ranges = AddrRange(0, 268435455))
system.sharedl1icache1 = icache_class(#clock = options.clock,
size = options.l1i_size,
assoc = options.l1i_assoc,
addr_ranges = AddrRange(268435456,536870911))
system.tol1icachebus = CoherentBus(clk_domain = system.cpu_clk_domain,
width = 32) #clock = options.clock, width = 32)
system.sharedl1icache0.cpu_side = system.tol1icachebus.master
system.sharedl1icache1.cpu_side = system.tol1icachebus.master
if options.l2cache != True:
print"sharedL1Icache requires a l2 cache, please configue it"
sys.exit(1)
system.sharedl1icache0.mem_side = system.tol2bus.slave
system.sharedl1icache1.mem_side = system.tol2bus.slave
I turned the debug flags on and found the assertion failing was caused by a snooping message for address 0x13081c0( in addrRange(0, 256MB)) on master port[1] of tol1icachebus. However, the master port[1] of tol1cachebus was configured to connected with sharedl1icache1 which has address range(256MB to 512MB). Therefore, the assertion failed.
Thanks for your reply!

在 2014年1月20日，下午4:31，Andreas Hansson <[email protected]> 写道：

Hi Kunta,

Did you manage to resolve this? Could you verify that you are using a CoherentBus?

From your diagram I do not see why it would not work, but there are some hidden assumptions around the port interactions between the o3 cpu/caches/bus that you might have stumbled upon.

If you’re still stuck on this I’d suggest running with the Bus and Cache debug flags to get some more insight.

Andreas

From: kunta Zhang <[email protected]>
Reply-To: gem5 users mailing list <[email protected]>
Date: Saturday, 21 December 2013 03:57
To: gem5 users mailing list <[email protected]>
Subject: [gem5-users] multi-port shared cache

I’m trying to configure a multi-port shared L1 cache among 4 cpus. The structure should look like this:

cpu0cpu1cpu2cpu3
| | | |
| | | | slave port of shared l1 bus
————————————————
shared l1 bus
————————————————
||
||master port of shared l1 bus
shared l1C0shared l1C1

I modified the python file to achieve this (assign each shared l1C with a different address range). However, the simulation ended with a message:
panic: system.tol1icachebus.master[0] was not expecting a timing snoop request

It seems that the snooping protocol do not approve two master ports.

Is there any convenient way to implement my structure?

Best，
Kunta Zhang
[email protected]

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ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782

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Re: [gem5-users] multi-port shared cache

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