Hi Kunta, Did you manage to resolve this? Could you verify that you are using a CoherentBus?
From your diagram I do not see why it would not work, but there are some hidden assumptions around the port interactions between the o3 cpu/caches/bus that you might have stumbled upon. If you’re still stuck on this I’d suggest running with the Bus and Cache debug flags to get some more insight. Andreas From: kunta Zhang <[email protected]<mailto:[email protected]>> Reply-To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Date: Saturday, 21 December 2013 03:57 To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Subject: [gem5-users] multi-port shared cache I’m trying to configure a multi-port shared L1 cache among 4 cpus. The structure should look like this: cpu0 cpu1 cpu2 cpu3 | | | | | | | | slave port of shared l1 bus ———————————————— shared l1 bus ———————————————— | | | |master port of shared l1 bus shared l1C0 shared l1C1 I modified the python file to achieve this (assign each shared l1C with a different address range). However, the simulation ended with a message: panic: system.tol1icachebus.master[0] was not expecting a timing snoop request It seems that the snooping protocol do not approve two master ports. Is there any convenient way to implement my structure? Best， Kunta Zhang [email protected]<mailto:[email protected]> -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
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