Hi all,
I'm trying to configure the LLC with stt-ram in the CMP architecture. Such
as 4 cores, 32KB L1 cache private, 4MB L2 cache shared. So the problem is how
to configure the LLC with stt-ram property. Which scripts should I modify?
Could you show me the configuration scripts or some suggestions?
I have read the codes in the file configs/common/Caches.py and tried to add
the read_latency and write_latency in the L2, but it failed.
If anyone has experienced the same issue , I would really appreciate to let
me know about it.
Thanks in advance.
Best Regards,
------------------
??????
Fanfan Shen PhD candidate
Computer School
Wuhan University,Wuhan,Hubei 430072,China
E-mail:[email protected]
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