Hello FanFan Shen, I am also working on modeling the last level cache as e-DRAM and STT-RAM. Please correct me if I am wrong as I figured out that the changes are to be made in the simpleDRAM.py, cache_impl.hh, simple_dram.hh/cc files for changing the DRAM technology parameters but I am not sure, whether by only changing the parameters in these files will lend up in modeling the L3 cache as e-DRAM or STT-RAM. Kindly let me know what are the additions and in what source files are to be done (if possible) and also whether the default configuration of the L1, L2 , L3 caches is a typical 6T-SRAM and whether is it different from the main memory configuration and how I can change it? The command --mem-type="XXXX" is used to specify the type for main memory only, am I right??
Any help or suggestion is appreciated. Thanks, Best Regards, Prateek _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
