Hi Cong Ma, You can look at this patch http://reviews.gem5.org/r/2072/, It will tell you how to modify the gem5 and then you know how to model different read/write latency. Hope this can help you.
Best regards, Fanfan Shen 于 04/22/2014 10:35 AM, fandroid 写道: > From: Cong Ma <embolon <at> gmail.com> > Subject:Re: Configure the last level cache(LLC) with stt-ram > <http://news.gmane.org/find-root.php?message_id=53447F4D.8070800%40gmail.com> > Newsgroups:gmane.comp.emulators.m5.users > <http://news.gmane.org/gmane.comp.emulators.m5.users> > Date: 2014-04-08 22:59:25 GMT (1 week, 6 days, 3 hours and 34 minutes ago) > 于 4/8/2014 2:37 PM, QI JIA 写道: > > 沈凡凡 <ffshen <at> whu.edu.cn> writes: > > > >> > >> Hi all, > >> I'm trying to configure the LLC with *stt*-*ram* in the CMP > >> architecture. > > Such as 4 cores, 32KB L1 cache private, 4MB L2 cache shared. So the problem > > is how to configure the LLC with *stt*-*ram* property. Which scripts should > > I > > modify? Could you show me the configuration scripts or some suggestions? > >> I have read the codes in the file configs/common/Caches.py and tried to > > add the read_latency and write_latency in the L2, but it failed. > >> If anyone has experienced the same issue , I would really appreciate to > > let me know about it. > >> > >> Thanks in advance. > >> Best Regards, > >> > >> > >> ------------------ > >> > >> 沈凡凡Fanfan Shen PhD candidateComputer SchoolWuhan University,Wuhan,Hubei > > 430072,ChinaE-mail:ffshen <at> whu.edu.cn > >> > >> Hi, I also work on this. For me, if you only care about write/read > > latency, you could configure it easily in BaseCache.py. Also do not forget > > differentiating read latency from write latency. > > > >> > >> _______________________________________________ > >> gem5-users mailing list > >> gem5-users <at> gem5.org > >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > > > > > _______________________________________________ > > gem5-users mailing list > > gem5-users <at> gem5.org > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > Hi Fanfan Shen, > > I am also interested in how to model different read and write latencies > in gem5. Could you be more specific on how to change BaseCache.py? > > Thank you, > > -- > Sincerely, > Cong Ma
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