? 04/22/2014 10:07 AM, fandroid ??:
Hi Prateek,
I am also new to use gem5 modeling LLC, so I have faced the same
problem with you. I am not sure how to configure LLC with STT-RAM, for
now I have modified gem5, I can set the LLC with different read/write
latency, I am not sure whether it's the right for the STT-RAM, If you
find the solution or make sure about it. Please let me know.
Any help or suggestions is appreciated,
Thanks in
? 04/09/2014 06:52 AM, [email protected] ??:
Date: Tue, 08 Apr 2014 12:21:03 -0700
From: Prateek Gupta<[email protected]>
To: gem5-users<[email protected]>
Subject: [gem5-users] Configure the last level cache(LLC) with stt-ram
Message-ID:<[email protected]>
Content-Type: text/plain; charset=iso-8859-1
Hello FanFan Shen,
I am also working on modeling the last level cache as e-DRAM and STT-RAM.?Please correct
me if I am wrong as I figured out that the changes are to be made in the simpleDRAM.py,
cache_impl.hh, simple_dram.hh/cc files for changing the DRAM technology parameters but I
am not sure, whether by only changing the parameters in these files will lend up in
modeling the L3 cache as e-DRAM or STT-RAM. Kindly let me know what are the additions and
in what source files are to be done (if possible) and also whether the default
configuration of the L1, L2 , L3 caches is a typical 6T-SRAM and whether is it different
from the main memory configuration and how I can change it? The command
--mem-type="XXXX" is used to specify the type for main memory only, am I right??
Any help or suggestion is appreciated.
Thanks,
Best Regards,
Prateek
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