Okay.....Actually I am making the decision of what frequency which core has to run, inside the cpu...
So I guess I have to somehow communicate this to the dvfs handler which doesn't look so clean.... Is there any other way around or hack anybody has done?? On Apr 15, 2015 10:14 AM, "Yahia Benmoussa" <yahia.benmou...@gmail.com> wrote: > Hello, > > Setting the required frequency in > /sys/devices/system/cpu/cpu*/cpufreq/scaling_setspeed should not be in gem5 > sources files. It can be done in a program (written in C, shell script or > any other language) > and running under Linux in FS mode. > > Regards > Yahia > > 2015-04-15 16:55 GMT+02:00 Nimish Girdhar <nimi...@tamu.edu>: > >> Thanks Yahia for sharing that. >> >> Can you explain a bit more as I don't have much experience with that. >> >> Let's say I have some algo to decide the cpu freq in gem5 >> SRC/CPU/O3/commit_impl.hh... How can I set the file you mentioned to that >> freq from here?? >> >> Thanks, >> On Apr 15, 2015 2:53 AM, "Yahia Benmoussa" <yahia.benmou...@gmail.com> >> wrote: >> >>> Hello, >>> >>> You have to enable userspace governor in your kernel then you can scale >>> the CPU frequency by setting >>> /sys/devices/system/cpu/cpu*/cpufreq/scaling_setspeed file. It should work. >>> >>> Regards. >>> Yahia >>> >>> >>> 2015-04-15 4:00 GMT+02:00 Nimish Girdhar <nimi...@tamu.edu>: >>> >>>> Hello all, >>>> >>>> I am working on a project where I have to use DVFS to change the >>>> frequency of cores based on my evaluation of some counters that I inserted >>>> in the gem5 o3 cpu src code. >>>> >>>> I followed the guidelines given on >>>> http://www.m5sim.org/Running_gem5#Experimenting_with_DVFS . >>>> But with these steps, the kernel will be the one who decides the >>>> performance levels of the cores at different point of time. But in my case >>>> I want to decide the levels based on some counters as mentioned above. >>>> >>>> Has anybody tried anything similar to that? I want to know how can I >>>> access and update the dvfs handler registers from within the cpu src code. >>>> >>>> Any help will be appreciated. >>>> >>>> Thanks, >>>> >>>> -- >>>> Warm regards >>>> Nimish Girdhar >>>> Department of Electrical and Computer Engineering >>>> Texas A&M University >>>> >>>> _______________________________________________ >>>> gem5-users mailing list >>>> gem5-users@gem5.org >>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>>> >>> >>> >>> _______________________________________________ >>> gem5-users mailing list >>> gem5-users@gem5.org >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>> >> >> _______________________________________________ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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