Andreas, I am trying to implement the SPARC T1 processor in GEM5. The Minor CPU doesn’t work for the SPARC ISA (https://www.mail-archive.com/gem5-users%40gem5.org/msg13256.html). But for my objective, I need to do detailed performance simulation for SPARC and generate power numbers in McPAT for the simulation.
Reading the paper, it seemed like it was easier to modify the O3 model rather than changing the InOrder (which is MinorCPU now) CPU according to the author. The reason I asked is, I have run the SPARC ISA on O3 CPU detailed simulation, but since it is Out of Order, it doesn’t necessarily represent the actual T1. Do I have any other reasonable options? Thanks Monir
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
