Andreas, I agree with you fully that T1 is old is almost not supported anywhere and I am facing the challenges pretty much at every step. ☹
But I have invested a lot of time and effort with T1 (I would like to achieve at-least some results for the efforts put into this). The reason for starting with T1 was, it is open source (OpenSPARC T1) and have the RTL available. There has also been some work done at the RTL level as well as Arch. Level (namely using Simics, which is no longer available). The other ISA choices mentioned does not have any readily available RTL codes (to my knowledge). Right now I DO NOT plan to run the GEM5 in FS mode as well. I just wanted to see if there was a way I could easily (relatively) achieve the “approximate” InOrder CPU behavior with the O3 CPU and then run the SPARC ISA in SE mode. ☹ I shall surely look into the RunTime Power modelling you suggested. /Monir
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