Hello Jason:
I have tag every transition in the cache controller (i.e.,
MESI_Three_Level-L0cache.sm) with the required resources, but there is
something wrong, during the
implementation of the L0 multi-bank, I have doubt whether need to add L1
RequestType? It also means require L1 cache resources.
for example:
transition(I, Ifetch, Inst_IS) {ITagArrayRead}{
pp_allocateICacheBlock;
i_allocateTBE;
a_issueGETS;
uu_profileInstMiss;
po_observeMiss;
k_popMandatoryQueue;
debugTransition1;
}
Instruction fetch missed in the L0, should I add L1TagArrayRead like this:
transition(I, Ifetch, Inst_IS) {ITagArrayRead, L1TagArrayRead}
Looking forward to your reply.
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