It looks like we don't have a statistic to track write-buffer occupancy. It occurred to me that the explanation doesn't involve that though... the issue is that with write-back caches, the only writes to main memory are cache block writebacks, and in our protocol, writebacks are not acknowledged (they can't be nacked, so once they're successfully sent they're guaranteed to complete). So since there's no response to a writeback, changing the write latency on main memory will have no effect.
This isn't completely realistic, but as long as your main memory can sustain writes at the bandwidth of the main memory bus, it's not too bad of a model. Steve On Mon, Jul 5, 2010 at 6:44 AM, sheng qiu <herbert1984...@gmail.com> wrote: > hi all, > > i used physicalmemory as the memory model for full system simulation. i > first set 30ns as the memory access latency, then i set 60ns as the memory > access latency. i found the missrate of running the same benchmark under > these two conditions has different results. the former one(30ns) has a > little larger missrate. i did understand why has different missrate. > > another thing is i want to has different write/read access time of > physicalmemory. so i set write request has 6X more access latency than read. > however i found no difference of sim_ticks with unchanged version under the > same benchmark and configurations. i know the write buffer may hide the > write latency, but anyone know how to see the occupancy of write buffer and > how to change the size of it? > > Thanks, > Sheng > > > _______________________________________________ > m5-users mailing list > m5-users@m5sim.org > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > _______________________________________________ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
