IBM published (Journal of R&D, or Systems Journal) a Formal Description
of the S/360 in APL. I recall, but do not have any concrete evidence,
that the writing of that work led to some changes in the machine
architecture. Better to ask one of the IBMers of the era.
There was also a book on logic circuit design somewhat later
that I can't find just now, which may be the one to which you are
alluding.
Bob
On Fri, 2007-10-19 at 03:23 +0000, dly wrote:
> This sounds much like the only book I could get on APL in the early
> 70's that described machine architecture using APL - maybe it is
> still in University libraries and maybe someone has a better memory
> of the title. It also might be available through ACM.
>
> Donna
> [EMAIL PROTECTED]
>
>
>
>
> On 18-Oct-07, at 4:58 PM, Arie Groeneveld wrote:
>
> > During the on going process of teaching myself J, I came
> > upon the idea of developing a lab on the subject of logic
> > circuits. As far as I know there's not much about this
> > subject, so may be it is of interest for some members
> > of the community.
> >
> > What I have so far is a short lab giving examples of
> > building simple logic circuits consisting of just one
> > basic element called a NAND GATE. For this moment the
> > lab offers the XOR GATE as most complex construction.
> > My intention is to extend this to more complex circuits
> > like a JK MS flipflop, a shift register, a full adder,
> > etc ..., if possible :-)
> >
> > I'm aware of the following facts:
> >
> > - My native language isn't English
> > - I'm not an expert in J; f.e. tacit
> > - ...
> >
> > Anyway, apart from these facts, and you will probably
> > come up with more, perhaps this simple lab could evolve
> > to a fully fledged member of the lab collection.
> >
> > It will be appreciated to give commentary and to judge
> > how to continue.
> >
> > The lab is attached as 'logiccircuits.ijt'
> >
> >
> > Regards
> >
> >
> > @@i
> >
> > p.s. If there already exists something on this
> > subject in the house of J, please let me know!
> >
> >
> > LABTITLE=: 'Logic circuits'
> > LABAUTHOR=: 0 : 0
> > A Groeneveld
> >
> > 2007
> > )
> > LABCOMMENTS=: 'Comments to [EMAIL PROTECTED]'
> > LABFOCUS=: 1
> >
> > NB. =========================================================
> > Lab Section INTRODUCTION
> >
> > In this lab we will learn to build simple logic circuits based on
> > one basic element. This basic element is called a NAND GATE and is
> > equipped with two input terminals and one output terminal. The
> > compelling starting point in building circuits shall be: you may
> > only use NAND GATES. It's the LAW! Of course you will need some basic
> > knowledge on boolean algebra and logic circuits.
> >
> > Boolean symbols:
> >
> > + OR
> > . AND
> > _
> > a not a
> >
> >
> > Some important boolean reductions used in transforming one boolean
> > function into another:
> >
> > a+a.b = a.1+a.b = a.(1+b) = a
> > _ _ _
> > a+a.b = a+a.b+a.b = a+b.(a+a) = a+b.1 = a+b
> >
> >
> > Boolean definition of the nand function:
> >
> > ___
> > nand = a.b
> >
> > Circuit:
> >
> > ____
> > a--| |
> > | & |o--> f
> > b--|____|
> >
> >
> > This function is defined with the J-primitive *:.
> > )
> >
> > NAND=: *:
> >
> > NB. input signals
> >
> > a=: 0 0 1 1
> > b=: 0 1 0 1
> >
> > NB. Truth table
> >
> > ('a b';'nand'),:(a,.b);,.a NAND b
> >
> > NB. =========================================================
> > Lab Section NOT GATE
> >
> > We can build a NOT GATE with one NAND GATE by connecting the two
> > inputs
> > with the single input signal.
> >
> >
> > _ ___
> > not = c = c.c
> >
> > ____
> > +---| |
> > c--+ | & |o-->
> > +---|____|
> > )
> >
> > NOT=: NAND~
> >
> > NB. input
> > c=: 0 1
> >
> > ('c';'not'),:(,.c);,.NOT c
> >
> > NB. =========================================================
> > Lab Section AND GATE
> >
> > Another basic circuit we can build is the AND GATE by connecting
> > two NAND GATES as follows:
> >
> > ___
> > ___
> > and = a.b = a.b
> >
> > We start with a NAND GATE with inputs a and b and then feeding
> > the output to an inverter (NOT GATE).
> >
> > ____ ____
> > a--| | +---| |
> > | & |o--+ | & |o-->
> > b--|____| +---|____|
> > )
> >
> > AND=: [:NAND~NAND
> >
> > ('a b';'and'),:(a,.b);,.a AND b
> >
> > NB. =========================================================
> > Lab Section OR GATE
> >
> > The following basic circuit is the OR GATE.
> >
> > If we look at the TT (truth table) we'll notice that only if
> > a and b are zero the output is zero:
> >
> > +---+--+
> > |a b|or|
> > +---+--+
> > |0 0|0 |
> > |0 1|1 |
> > |1 0|1 |
> > |1 1|1 |
> > +---+--+
> >
> > In other words: if not not a and not b => f = 1
> >
> > ___ ___
> > ___ _ _
> > or = a+b = a+b = a.b
> >
> > So the OR GATE is constructed by inverting both inputs (NOT GATES) and
> > feeding the outputs to a NAND GATE.
> >
> > ____
> > a +-| |
> > | | & |o--+ ____
> > +-|____| +--| |
> > ____ | & |o-->
> > b +-| | +--|____|
> > | | & |o--+
> > +-|____|
> > )
> >
> > OR=: ([:NAND~[)NAND[:NAND~]
> >
> > ('a b';'or'),:(a,.b);,.a OR b
> >
> > NB. =========================================================
> > Lab Section
> >
> > Exercise
> >
> > Find one or more alternatives for the OR GATE by playing with
> > boolean algebra. An example will follow hereafter.
> > )
> >
> > NB. =========================================================
> > Lab Section
> >
> > Here's an example for an alternative construction.
> > _____ _____
> > _____ _ ___
> > _ _ _
> > OR = a+b = a+a.b = a+a.b = a.a.b
> >
> >
> > ____
> > a+--| | ____
> > | | & |o--+------------| |
> > +--|____| | ____ | & |o-->
> > +--| | +-|____|
> > | & |o-+
> > b---------------|____|
> > )
> >
> > ORA=: 4 : '(x&NAND NAND ]) NAND~y'
> >
> > ('a b';'or'),:(a,.b);,.a ORA b
> >
> > a (ORA-:OR) b
> >
> > NB. =========================================================
> > Lab Section NAND GATE with 3 inputs
> >
> > If we need a NAND with 3 inputs:
> > _____ _______
> > _____ _____
> > _____ _____ _ _____ _ _____
> > nand = a.b.c = (a.b)+c = (a.b)+c = (a.b).c
> >
> > Connecting two of the input signals to an AND GATE (constructed with
> > NAND GATES!) and then feeding this output together with the third
> > input to another NAND GATE.
> >
> > ____ ____
> > a--| | +---| |
> > | & |o--+ | & |o--+ ____
> > b--|____| +---|____| +-| |
> > | & |o-->
> > c--------------------------|____|
> >
> > Here we depart from the dyadic approach so far by using a boxed noun
> > containing the three input signals. So this NAND will be a monadic
> > verb.
> > )
> >
> > NAND3=: 3 : 0
> > 'a b c'=. y
> > c NAND NAND~ a NAND b
> > )
> >
> > NB. triple input
> > p=: 0 0 0 0 1 1 1 1
> > q=: 8$0 0 1 1
> > r=: 8$0 1
> >
> > ('p q r';'nand'),:(p,.q,.r);,.NAND3 p;q;r
> >
> > NAND3 (?10$2);(?10$2);?10$2
> >
> > NB. =========================================================
> > Lab Section XOR GATE
> >
> > A bit more complex circuit is the XOR GATE. Using five NAND GATES we
> > are able to construct this GATE. The xor-function with inputs a and b
> > is defined as:
> >
> > _______ _______
> > _______ ___ ___
> > _ _ _ _ _ _
> > xor = a.b+a.b = a.b+a.b = a.b.a.b
> >
> >
> > ____
> > a-+-| | ____
> > | | & |o----| |
> > +-|____| | & |o---+
> > b--------------|____| | ____
> > +--| |
> > ____ | & |o-->
> > b-+-| | ____ +--|____|
> > | | & |o----| | |
> > +-|____| | & |o---+
> > a--------------|____|
> > )
> >
> > XOR5 =: (NAND NAND~)NAND]NAND NAND~
> >
> > ('a b';'xor'),:(a,.b);,.a XOR5 b
> >
> > NB. =========================================================
> > Lab Section
> >
> > A reduction in hardware can be made by building the XOR GATE with
> > only four NAND GATES.
> >
> > _ _
> > xor = a.b+a.b
> >
> >
> > By repeatedly applying double inverting and the laws of the Morgan
> > we can derive:
> >
> > _______ _______ _______
> > _______ ___ ___ ___________ ___ ___
> > _ _ _ _ _ _ _ _ ___ ___
> > xor = a.b+a.b = a.b+a.b = a.b.a.b =(a+b).(a+b) =a+b.a+b
> >
> > _______________
> > _______ _______ ___________
> > _______ _______ _____ _____
> > _ _ ___ ___
> > = (a.b+b).(a+a.b) = a.b.b.a.a.b
> >
> >
> > Giving the following circuit:
> > ____
> > a--| |
> > | & |o--+
> > +-|____| |
> > ____ | | ____
> > a--| | | +--| |
> > | & |o--+ | & |o-->
> > b--|____| | +--|____|
> > | ____ |
> > +-| | |
> > | & |o--+
> > b--|____|
> > )
> >
> > XOR=: 4 : '(x&NAND NAND y&NAND) x NAND y'
> >
> > ('a b';'xor'),:(a,.b);,.a XOR b
> >
> > NB. random input signals
> >
> > ] x=: ?10$2
> >
> > ] y=: ?10$2
> >
> > ('x y';'xor'),:(x,.y);,.x XOR y
> >
> >
> > ----------------------------------------------------------------------
> > For information about J forums see http://www.jsoftware.com/forums.htm
>
> ----------------------------------------------------------------------
> For information about J forums see http://www.jsoftware.com/forums.htm
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