On 25/04/08 00:35, Tristan Gingold wrote:
> it seems clocker.vhdl is missing!
>
Oops! sorry, here is the clock generation module.
SET
--
_______________________________________________________________
Ing. Salvador Eduardo Tropea http://utic.inti.gov.ar/
INTI-Electrónica e Informática Tel: (+54 11) 4724 6315
Colectora de Av. General Paz 5445 San Martín - B1650KNA
Casilla de Correo 157 FAX: (+54 11) 4754 5194
Buenos Aires * Argentina http://www.inti.gov.ar/
--
_______________________________________________________________
Ing. Salvador Eduardo Tropea http://utic.inti.gov.ar/
INTI-Electrónica e Informática Tel: (+54 11) 4724 6315
Colectora de Av. General Paz 5445 San Martín - B1650KNA
Casilla de Correo 157 FAX: (+54 11) 4754 5194
Buenos Aires * Argentina http://www.inti.gov.ar/
library IEEE;
use IEEE.std_logic_1164.all;
entity Clocker is
generic(
FREQUENCY : positive:=12 -- Clock freq. MHz
);
port(
clk_o : out std_logic; -- System clock
clk6_o : out std_logic -- 6 MHz
);
end entity Clocker;
architecture Simul of Clocker is
constant DIV : positive:=FREQUENCY/6;
signal clk : std_logic:='0';
signal clk6 : std_logic:='0';
begin
sclock:
process
begin
clk <= not(clk);
wait for (1 us)/(2*FREQUENCY);
end process sclock;
clk_o <= clk;
mult6:
process
begin
assert (FREQUENCY mod 6)=0 report "FREQUENCY should be multiple of 6"
severity warning;
wait;
end process mult6;
clk6MHz:
process (clk)
variable cnt : integer range 0 to DIV-1:=0;
begin
if rising_edge(clk) then
if cnt=DIV-1 then
clk6 <= '1';
cnt:=0;
else
clk6 <= '0';
cnt:=cnt+1;
end if;
end if;
end process clk6MHz;
clk6_o <= clk6;
end architecture Simul; -- Entity: Clocker
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