On Wed, Apr 23, 2008 at 01:35:01PM -0300, Salvador Eduardo Tropea wrote:
> Hi all!
> 
> We switched to 0.26 seven weeks ago and we stated to notice some strange
> effects.
> It looks like 0.26 have some problems with the evaluation order or the
> delta time stuff. I'm not sure how to describe it, but looks like some
> conditions are evaluated before/after the signals settle down to their
> corresponding value.
> The first problem we saw was warnings from numeric_std at t=0, we tried
> to fix them initializing every single signal, we finally realized it was
> imposible to solve them. Now I faced another similar thing: a logic
> operation carried out at some level in the hierarchy strangely failed,
> when moved to the child block it started to work as expected. I added
> some reports to the VHDL and they exposed an inconsistency.
> Is anybody experimenting similar problems?

Hi,

if you have a small reproducer, it would be useful.

Tristan.

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