On Thu, Apr 24, 2008 at 11:26:24AM -0300, Salvador Eduardo Tropea wrote: > Hi Tristan and all in the list: > > It wasn't easy to isolate the problem but I was able to create a simple > set of 8 sources that reproduce the problem. > The real application is a full USB core (PHY, SIE and Function, all in > the same IP and using hard, no firmware). > I hope I included all the needed files, tell me if something is missing.
Hi, also note that Level2 will delay phy_clk by 1 delta. I still need clocker to fully understand and analyze your case. Tristan. _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
