Hi all! We switched to 0.26 seven weeks ago and we stated to notice some strange effects. It looks like 0.26 have some problems with the evaluation order or the delta time stuff. I'm not sure how to describe it, but looks like some conditions are evaluated before/after the signals settle down to their corresponding value. The first problem we saw was warnings from numeric_std at t=0, we tried to fix them initializing every single signal, we finally realized it was imposible to solve them. Now I faced another similar thing: a logic operation carried out at some level in the hierarchy strangely failed, when moved to the child block it started to work as expected. I added some reports to the VHDL and they exposed an inconsistency. Is anybody experimenting similar problems?
Regards, SET -- _______________________________________________________________ Ing. Salvador Eduardo Tropea http://utic.inti.gov.ar/ INTI-Electrónica e Informática Tel: (+54 11) 4724 6315 Colectora de Av. General Paz 5445 San Martín - B1650KNA Casilla de Correo 157 FAX: (+54 11) 4754 5194 Buenos Aires * Argentina http://www.inti.gov.ar/ _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
