Hello Jonas, here is a short way to convert a FSM encoding to a binary representation for an FPGA internal logic analyzer:
function dbg_EncodeState(st : T_STATE) return std_logic_vector is
begin
return std_logic_vector(unsigned(T_STATE'pos(st),
log2ceilnz(T_STATE'pos(T_STATE'high) + 1)));
end function;
-- log2ceilnz computes: logarithm for base 2 (log2) with always round-up (ceil)
and the result is never zero (nz)
-- ...
ILA1_data(3 downto 0) <= dbg_EncodeState(CurrentState);
You can go even a step further and convert every enum member name into a string
and write it as a Token-file
to disk for importing it into your logic analyzer, to it will display names
instead of binary state values:
function dbg_GenerateStateEncodings return string is
variable l : STD.TextIO.line;
begin
for i in T_STATE loop
STD.TextIO.write(l, str_replace(T_STATE'image(i), "st_", ""));
STD.TextIO.write(l, ';');
end loop;
return l.all;
end function;
-- str_replace removes a common prefix from all member names
constant dummy : Boolean := dbg_ExportEncoding("Link Layer - FSM",
dbg_GenerateStateEncodings, PROJECT_DIR &
"ChipScope/TokenFiles/FSM_LinkLayer.tok");
Source: https://github.com/VLSI-EDA/PoC/blob/master/src/common/debug.vhdl
> I believe I should create a new topic in eda-twiki.org instead.
As pointed out there are existing proposals. Maybe one is already close to your
ideas / imagination, then there is no need to write a new one. Just add your
thoughts or propose improvements or contact the author to review / enhance his
proposal.
-----------------------------------
Wissenschaftliche Hilfskraft
Technische Universität Dresden
Fakultät Informatik
Institut für Technische Informatik
Lehrstuhl VLSI-Entwurfssysteme, Diagnostik und Architektur
01062 Dresden
-----Original Message-----
From: Ghdl-discuss [mailto:ghdl-discuss-boun...@gna.org] On Behalf Of Jonas
Baggett
Sent: Thursday, July 28, 2016 8:35 PM
To: GHDL discuss list <ghdl-discuss@gna.org>
Subject: Re: [Ghdl-discuss] Better way for integer handling in VHDL ?
Hello Patrick,
> I was just saying that VHDL has capabilities to create bigger integer
> numbers. That doesn't imply that I like or teach that one should use
> INTEGERs for hardware design. I'm using INTEGERs only for constants
> and generic parameters. Even if you could specify a new integer with
> the range of a 64-, 128- or 256-bit INTEGER, that's not enough for some
> calculations. So a SIGNED/UNSIGNED might be more flexible.
I misunderstood you. My whold point was about how could we enhance INTEGERs so
that they could supercede the IEEE signed/unsigned types for hardware design,
so that it leads to more human readable code.
> You can specify enum and FSM encoding in VHDL by using attributes.
> Unfortunately, these attribute names and their content is not specified, but
> most vendors and tools use similar names.
>
> attribute fsm_encoding : string;
> attribute fsm_encoding of state : signal is "gray";
>
> or
>
> attribute enum_encoding : string;
> attribute enum_encoding of My_FSM : type is "001 010 110"; attribute
> fsm_encoding : string; attribute fsm_encoding of state : signal is
> "user"; -- use the encoding of state's type
Ok. Actually once in a project I needed to convert a FSM to std_logic_vector in
order to display it in a logic analyzer once synthetized for debugging purpose.
So I needed to use a with select clause to do the conversion while with this
'Logic attribute I could just use the 'Logic attribute of the signal. But, yes
most of the time we don't need FSM type <-> std_logic_vector conversion and
then we can live without this 'Logic attribute on enum types, but it was just
to show that this feature is generalizable.
> Are you referring to the bit-order (MSB/LSB on right/left)?
> This is solved by VHDLs to/downto ranges.
Yes, exactly.
Now I am thinking that this mailing-list may not be the best place to speak
about possible enhancements to VHDL.
I believe I should create a new topic in eda-twiki.org instead.
Bye,
Jonas
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