@cousteaulecommandant pushed 2 commits. a5dcc9d218c69f07171d3ba346c5b2c3ab84ff8e Add missing SystemVerilog tasks/functions eec080af505f143bfdd8a98d6d83b7350cc9fa7c Regenerate Verilog ctags unit tests
-- View it on GitHub: https://github.com/geany/geany/pull/4039/files/26dc1eca5fbd522fa1d27a43605bb0a0092060ce..eec080af505f143bfdd8a98d6d83b7350cc9fa7c You are receiving this because you are subscribed to this thread. Message ID: <geany/geany/pull/4039/before/26dc1eca5fbd522fa1d27a43605bb0a0092060ce/after/[email protected]>
