Um Hayes, they are doing that.
reference: Merom, Conroe, Woodcrest
64bit 65nm chips due in the middle of '06, 14 stage pipelines, 2-3Ghz
clocks, 4-issue dispatch! (A64s are 3 issue, G5s are 3+branch, P4's are
2-issue)
Pentium M is P3 derived, and lacks the 64bitness, rather that futz around
giving it a 64bit overhaul, they're designing something based on a
similar philosophy from the ground up..
Yes, but Yonah and later PM cores have an extra 4-cycle latency on the L2
cache. Hopefully, this can be disabled at will....it comes from the core's
ability to shut down cache areas that aren't needed and flush contents to
memory.
This does necessarily hurt the performance per MHz, but it is still very
competitive.
Greg
