> >there is a technique called "PSW scrunching" that allows saving an extended > >PSW in a normal 8 byte PSW field when the instruction address is only 4 > >bytes. > > > That implies, doesn't it, that in addition to the top 32 bits of the > instruction address, 32 other bits in the 128-bit PSW are irrelevant > and can be scrunched away? Hmmm... AMODE(31) goes back into bit 0 > of 32, just like XA? And AMODE(64) into bit 31? It's a Good Thing > that no one (well, not many) ever used bit 31 to bootleg one more flag. > > But still, are there so many control blocks that need to store the > PSW in 64 bits, but needn't store 64 bit registers? Those can't > be scrunched.
In current z/Architecture, PSW.33-63 must be 0. PSW.32 (BA) of a 128-bit PSW gets scrunched into PSW.32 (A) of a 64-bit PSW. PSW.31 (EA) of a 128-bit PSW remains at PSW.31 of a 64-bit PSW when scrunching. This is in accordance with definition of LPSW in z/Architecture. MVS has supported 64-bit registers in z/Architecture mode since OS/390 V2R10. Jim Mulder z/OS System Test IBM Corp. Poughkeepsie, NY ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
