On Mon, 1 Dec 2008 14:24:11 -0500, Shmuel Metz (Seymour J.) <[EMAIL PROTECTED]> wrote: >Were IBM to document it, the timing manual for any of the current >processors would be immense.
Nah. Page 1: "It depends". Page 2 would be intentionally left blank. With instruction pipelining, too much depends on what has happened *before* the instruction in question. From a raw technology perspective, changes in cache design and memory structure can affect an instruction as well (for good or ill). As was said, write your programs for readability and maintainability. Follow traditional rules about operand alignment. Do try to use RI-format instructions like LOAD HALFWORD IMMEDIATE to avoid storage reference or address generation. Alan Altmark z/VM Development IBM ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
