On Sat, 6 Dec 2025 at 15:53, Binyamin Dissen < [email protected]> wrote:
> Does the cache get flushed if, for example, SAM31 is issued when currently > in > 31 bit mode or if SAC 512 is issued when in AR mode? > I think the cases are different. For SAC, the PofO says "a serialization and checkpoint-synchronization function *is *performed before the operation begins and again after the operation is completed", and there is no "model-dependant" wording. I don't see that they can fast-path (i.e. skip) these in the "SAC-to-current" case, because the lack of the checkpoint-synchronization might in theory be detectable by the program. SAM, on the other hand, doesn't seem to do anything very expensive in any case. There is no cache flush or checkpoint-synch or whatever you want to call it - there is just checking of current PSW addressing bits (which is surely cheap) to avoid interpreting the NSI address in a too narrow addressing mode and effectively doing a wild branch. They could skip that without having to say so in the "SAM-to-current" case because it's undetectable. But by the same token, it's useless. Maybe they do, and maybe they don't, but I'd be very surprised if they bothered. What is the cost of an SAM just to be safe? > It looks very cheap to me. Unlike SAC. In passing, I've seen software that issues SAC 0 / SAC 512 many many times more often than it needs to, i.e. it really doesn't bother to keep track of the current mode. The world didn't fall apart performance-wise. Needless to say, this is just my interpretation of the PofO, which is probably no better than yours. Tony H. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
