On Sat, 6 Dec 2025 22:39:51 -0500, Tony Harminc <[email protected]> wrote:
>On Sat, 6 Dec 2025 at 15:53, Binyamin Dissen wrote: >> Does the cache get flushed if, for example, SAC 512 is issued when in AR >> mode? > >For SAC, the PofO says "a serialization and checkpoint-synchronization >function *is *performed before the operation begins and again after the >operation is completed" Hardware serialize (cpu) and checkpoint doesn't cause cache to be flushed otherwise 32MB L2 cache wouldn't be useful. Instead, checkpoint commits cache changes to storage. I suspect CPU serialization is required for checkpoint to guarantee multiple cores aren't committing the same cache at the same time. Think of this in terms of the "compare & swap" instruction. Checkpoint is caused by various instructions (PC, SVC, ...), interrupts, checkpoint interval and more. >I don't see that they can fast-path (i.e. skip) these in the "SAC-to-current" >case, >because the lack of the checkpoint-synchronization might in theory be >detectable by the program. Cache checkpoint is a hardware feature. Why would a program need to detect it? ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
