On Mon, 8 Dec 2025 04:00:08 +0000, James Mulder <[email protected]> wrote:
>In practice, on Z machines, it delays the CPU until all prior stores >have made it out of the CPU's store buffer and into the cache hierarchy, >which is where memory coherency is implemented. POPs says "storage" but I suspected memory coherency was at the cache level. I'm guessing this is at the L1 cache level because each CPU core has an independent L1 and L2 cache for each core. > From a programming point of view, a serialization function delays the CPU >on which is it occurring until all previous stores done on that CPU are >visible to other CPUs. When you say CPU, do you mean CPU core, CPU chip or CPU drawer? >So if you have some reason that you don't want your program to proceed until >it knows that > if another CPU access storage it has stored to, the other CPU will see the > values > this CPU has stored (and not some prior contents of the storage), >you issue an instruction which performs a serialization function. I believe this is the purpose of BR R0 performing serialization. > In practice, the engineers tell me that the processors are aggressive about > pushing out the stores. Will the processor bypass serialization when pushing out to the stores if the active instructions are not modifying the data being pushed? ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
