[email protected] (Bernd Oppolzer) writes: > I could imagine some use cases for a new instruction, that supresses > the execution of the next instruction, depending on certain values of the > condition code. For example SKIP NEXT INSTRUCTION IF NOT ZERO, > or IF ZERO. > > This would be much more general than "store on condition", because you > could skip every instruction (not only ST), depending on the condition > code. > > Of course, this needs some extensions to the machine logic, because it > must be possible that only the PSW will be incremented but the instruction > is not executed, depending on this SKIP condition. But: it saves some > branches in some cases. > > My question is: if we had such an instruction, how would this fit into > the overall machine concept? And: are there some performance benefits, > or are there some problems with this approach, which I do not see?
note this is compare-and-swap ... not done for instruction efficiency but serialized atomic operation (CAS are charlie's initials, done when he was working on fine-grain cp67 multiprocessor kernel locking, initial attempts to get it included in 370 were rebuffed by the pok favorite son operating system engineers; challenge was to come up with uses other than just kernel fine grain locking, examples still are included in principles of operation). one of the major areas of throughput improvement is superscalar and out-of-order execution (basically hardware equivalent of multitasking/multiprogramming to compensate for long delays for memory access on cache misses ... aka latency to memory measured in processor cycles is on the order of 360 disk acces time measured in 360 processor cycles). this has been common in some other architectures for decades ... but recently shows up in transition from z10 to z196 (on the order of half the per processor thruput increase) and additional throughput in z196 to ec12. big problem for out-of-order execution is conditional branches (or any operation dependent on condition). technology approach is branch prediction (attempts to predict which way condition will go) and speculative execution (go ahead and perform conditional operations ... and if the condition turns out not to perform those operations ... undo/abrogate). Strictly serialized instruction execution would have each additional instruction resulting in incremental elapsed time. for out-of-order execution, unconditional branch may be little different than straight sequential execution (modulo increased probability of cache miss). Any conditional operation becomes an issue how early is the condition determined. Some compiler technologies attempt to place condition setting as early as possible with as many (non condition setting) instructions as possible between when the condition is set and when the conditional operation occurs. there is also register "renaming" where there are more real hardware registers than addressable registers ... speculative execution can proceed concurrently on different possible conditional paths ... with possible different values for the same (addressable) registers. also speculative execution store operation have to be held in abeyance until it is known whether it is the valid path or they are to be discarded. there is theory work on "code density" ... especially for smaller machines with smaller instruction caches ... improvements in instruction architecture that signifcantly reduces the total bytes of instructions for a program. -- virtualization experience starting Jan1968, online at home since Mar1970 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
