On Mon, Feb 17, 2014 at 6:34 PM, Bernd Oppolzer
<[email protected]>wrote:
> Hello,
>
> when we discussed the one bit copy topic recently, I had a solution
> in mind that was kind of inspired by the new "store on condition"
> instruction,
> but there was no such solution, because a instruction like "OI on
> condition"
> or "NI on condition" would have been necessary, and there are no such
> instructions.
>
> Now my question:
>
> I could imagine some use cases for a new instruction, that supresses
> the execution of the next instruction, depending on certain values of the
> condition code. For example SKIP NEXT INSTRUCTION IF NOT ZERO,
> or IF ZERO.
>
> This would be much more general than "store on condition", because you
> could skip every instruction (not only ST), depending on the condition
> code.
>
> Of course, this needs some extensions to the machine logic, because it
> must be possible that only the PSW will be incremented but the instruction
> is not executed, depending on this SKIP condition. But: it saves some
> branches in some cases.
>
> My question is: if we had such an instruction, how would this fit into the
> overall machine concept? And: are there some performance benefits,
> or are there some problems with this approach, which I do not see?
>
> I'm sure, that some historical machines had such concepts ...
>
> Kind regards
>
> Bernd
>
>
>
I was thinking of something similar, but from the other side. An "execute
on condition" type instruction. It would be like the EX and EXRL
instructions, except that: where they have the R1 field, which designates
the register used to modify the EXecuted instruction, the EXConditional
would have an M1 field like the mask in the Branch instructions which says
whether the instruction pointed to by the second operand is executed
(unmodified) or not. I don't know how the machines actually work inside
(hardwired and millicoded instructions), but it seems to me that an EXC
might use some of the same hardware functionality.
Your "skip" could be implemented if IBM did an EXCI (not the CICS EXCI)
which would be an "EXecute Conditional Immediate". I'm just a bit concerned
about the possibility of the EXecuted immediate instruction getting a
program interrupt, such as a page fault. I don't know how tricky the
instruction decoding would need to be. With an EXCI, the next instruction
could be 2, 4, or 6 bytes and so the IC would need to be incremented by the
proper amount. With the EXC (or EXCRL), the instruction length is always 4
or 6 bytes, so updating the PSW address for the next instruction is a fixed
amount.
I also had the same thought about how well this would fit in and also
whether it was "worth it" in terms of hardware cost to develop and test. I
never did really come up with any good example to show how this would be
really useful. I saw a wonderful ARM code sequence in their assembler to
compute the GCD of a number. It was 5 assembler instructions.
Unfortunately, it used another ARM difference in that the ARM subtract
instruction can set the CC or not as desired by the programmer. And this
code depends on the subtract _not_ disturbing the CC set by the initial
compare.
GCD CMP R0,R1
SUBGT R0,R0,R1 IF GT FROM CMP THEN R0-=R1
SUBLT R1,R1,R0 IF LT FROM CMP THEN R1-=R0
BNE GCD IF NOT EQUAL FROM CMP THEN LOOP
; R0 CONTAINS GCD
The SUBGT and SUBLT don't disturb the condition code from the CMP. The z
doesn't have a way do go general arithmetic which doesn't set the condition
code. Yes, it could be done with the IPM and a couple of SPMs, I guess
GCD CR R0,R1
IPM R14
EXC SUB01,GT
SPM R14
EXC SUB10,LT
SPM R14
JNE GCD
---
SUB01 SR R0,R1
SUB10 SR R1,R0
But that doesn't really look that nice to me. I was looking for a "golly,
wiz! that is fantastic!" but couldn't think of any.
--
Wasn't there something about a PASCAL programmer knowing the value of
everything and the Wirth of nothing?
Maranatha! <><
John McKown
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