>From Wiki: Z12 chipset: Description[_edit_ (http://en.wikipedia.org/w/index.php?title=IBM_zEC12_(microprocessor)&action=edit§ion=1) ] The chip measures 597.24 mm2 and consists of 2.75 billion _transistors_ (http://en.wikipedia.org/wiki/Transistor) fabricated in IBM's _32 nm_ (http://en.wikipedia.org/wiki/32_nm) _CMOS_ (http://en.wikipedia.org/wiki/CMOS) _silicon on insulator_ (http://en.wikipedia.org/wiki/Silicon_on_insulator) _fabrication process_ (http://en.wikipedia.org/wiki/Semiconductor_device_fabrication) , supporting speeds of 5.5 _GHz_ (http://en.wikipedia.org/wiki/GHz) , the highest clock speed CPU ever produced for commercial sale._[3]_ (http://en.wikipedia.org/wiki/IBM_zEC12_(microprocessor)#cite_note-RedBookTechIn tro-3) The processor implements the _CISC_ (http://en.wikipedia.org/wiki/Complex_instruction_set_computer) _z/Architecture_ (http://en.wikipedia.org/wiki/Z/Architecture) with a _superscalar_ (http://en.wikipedia.org/wiki/Superscalar) , _out-of-order_ (http://en.wikipedia.org/wiki/Out-of-order_execution) _pipeline_ (http://en.wikipedia.org/wiki/Instruction_pipeline) and some new _instructions_ (http://en.wikipedia.org/wiki/Instruction_(computer_science)) mainly related to _transactional execution_ (http://en.wikipedia.org/wiki/Software_transactional_memory) . The cores have numerous other enhancements such as better branch prediction, out of order execution and one dedicated co-processor for compression and cryptography. The instruction pipeline has 15 to 17 stages; the instruction queue can hold 40 instructions; and up to 90 instructions can be "in flight". It has six _cores_ (http://en.wikipedia.org/wiki/Multi-core) , each with a private 64 _KB_ (http://en.wikipedia.org/wiki/Kilobyte) _L1 instruction cache_ (http://en.wikipedia.or g/wiki/CPU_cache) , a private 96 KB L1 data cache, a private 1 _MB_ (http://en.wikipedia.org/wiki/Megabyte) _L2 cache_ (http://en.wikipedia.org/wiki/CPU_cache) instruction cache, and a private 1 MiB L2 data cache. In addition, there is a 48 MB shared L3 cache implemented in _eDRAM_ (http://en.wikipedia.org/wiki/EDRAM) and controlled by two on-chip L3 cache controllers. There's also an additional shared L1 cache used for compression and cryptography operations. Each core has six _RISC_ (http://en.wikipedia.org/wiki/Reduced_instruction_set_computing) -like execution units, including two _integer units_ (http://en.wikipedia.org/wiki/Arithmetic_logic_unit) , two _load-store units_ (http://en.wikipedia.org/wiki/Load-store_unit_(computing)) , one binary _floating point unit_ (http://en.wikipedia.org/wiki/Floating-point_unit) and one _decimal floating point_ (http://en.wikipedia.org/wiki/Decimal_floating_point) unit. The zEC12 chip can decode three instructions and execute seven operations in a single clock cycle._[4]_ (http://en.wikipedia.org/wiki/IBM_zEC12_(microprocessor)#cite_note-RedBookTechGuide-4) Attached to each core is a special co-processor accelerator unit; in the previous z CPU there were two shared by all four cores. The zEC12 chip has on board multi-channel _DDR3 RAM_ (http://en.wikipedia.org/wiki/DDR_SDRAM) _memory controller_ (http://en.wikipedia.org/wiki/Memory_controller) supporting a _RAID_ (http://en.wikipedia.org/wiki/RAID) like configuration to recover from memory faults. The zEC12 also includes two _GX bus_ (http://en.wikipedia.org/wiki/PowerPC_600#6XX_and_GX_buses) controllers for accessing host channel adapters and peripherals. Z10: Description[_edit_ (http://en.wikipedia.org/w/index.php?title=IBM_z10_(microprocessor)&action=edit§ion=1) ] The processor implements the _CISC_ (http://en.wikipedia.org/wiki/Complex_instruction_set_computer) _z/Architecture_ (http://en.wikipedia.org/wiki/Z/Architecture) and has four _cores_ (http://en.wikipedia.org/wiki/Multi-core) . Each core has a 64 _KB_ (http://en.wikipedia.org/wiki/Kilobyte) _L1 instruction cache_ (http://en.wikipedia.org/wiki/CPU_cache) , a 128 KB L1 data cache and a 3 _MB_ (http://en.wikipedia.org/wiki/Megabyte) _L2 cache_ (http://en.wikipedia.org/wiki/CPU_cache) (called the L1.5 cache by IBM). Finally, there is a 24 MB shared L3 cache (referred to as the L2 cache by IBM). The chip measures 21.7×20.0 mm and consists of 993 million _transistors_ (http://en.wikipedia.org/wiki/Transistor) fabricated in IBM's _65 nm_ (http://en.wikipedia.org/wiki/65_nm) _SOI_ (http://en.wikipedia.org/wiki/Silicon_on_insulator) _fabrication process_ (http://en.wikipedia.org/wiki/Semiconductor_device_fabrication) (CMOS 11S), supporting speeds of 4.4 _GHz_ (http://en.wikipedia.org/wiki/GHz) and above – more than twice the clock speed as _former mainframes_ (http://en.wikipedia.org/wiki/IBM_System_z9) – with a 15 _FO4_ (http://en.wikipedia.org/wiki/FO4) cycle. Each z10 chip has two 48 _GB_ (http://en.wikipedia.org/wiki/Gigabyte) /s (48 billion _bytes_ (http://en.wikipedia.org/wiki/Byte) per second) SMP hub ports, four 13 GB/s memory ports, two 17 GB/s I/O ports, and 8765 contacts. The z10 processor was co-developed with and shares many design traits with the _POWER6_ (http://en.wikipedia.org/wiki/POWER6) processor, such as fabrication technology, logic design, _execution unit_ (http://en.wikipedia.org/wiki/Execution_unit) , floating-point units, bus technology (_GX bus_ (http://en.wikipedia.org/wiki/PowerPC_600#6XX_and_GX_buses) ) and _pipeline_ (http://en.wikipedia.org/wiki/Instruction_pipeline) design style, i.e., a high frequency, low latency, deep (14 stages in the z10), in-order pipeline. However, the processors are quite dissimilar in other respects, such as cache hierarchy and _coherency_ (http://en.wikipedia.org/wiki/Cache_coherency) , _SMP_ (http://en.wikipedia.org/wiki/Symmetric_multiprocessing) topology and protocol, and chip organization. The different _ISAs_ (http://en.wikipedia.org/wiki/Instruction_set) result in very different cores – there are 894 unique z10 instructions, 75% of which are implemented entirely in hardware. The z/Architecture is a _CISC_ (http://en.wikipedia.org/wiki/Complex_instruction_set_computer) architecture, backwards compatible to the _IBM System/360_ (http://en.wikipedia.org/wiki/IBM_System/360) architecture from the 1960s. Additions to the z/Architecture from the previous _z9 EC_ (http://en.wikipedia.org/wiki/IBM_System_z9) processor include: * 50+ new instructions for improved code efficiency * software/hardware cache optimizations * support for 1 MB page frames * decimal floating point fully implemented in hardware. Error detection and recovery is emphasized, with _error-correcting code (ECC)_ (http://en.wikipedia.org/wiki/Error_detection_and_correction#Error-correcting_code) on L2 and L3 caches and buffers, and extensive parity checking elsewhere; in all over 20,000 error checkers on the chip. Processor state is buffered in a way that allows precise core retry for almost all hardware errors. In a message dated 6/10/2014 1:54:18 P.M. Central Daylight Time, [email protected] writes:
Moore's Law: "The number of transistors incorporated in a chip will approximately double every 24 months." ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
