On Thu, 11 Feb 2016 09:26:00 -0600, Paul Gilmartin <[email protected]> wrote:
>On Thu, 11 Feb 2016 05:39:33 -0600, Tom Marchant wrote: >> >>For example, z/Architecture uses 64-bit addresses, so all of those places >>where an >>address is defined are 64 bits wide. PSW address is an obvious one. Also, the >>locations >>for the old and new PSW for SVC, I/O, External, Restart, Machine Check, and >>Program >>interruptions now require 16 bytes. Dynamic Address Translation tables (page >>and >>segment tables, etc.) require 64 bits for addresses. Likewise for Control >>registers. >> >Does this imply no more scrunched PSWs? Execution above the bar becomes >possible? >64-bit LPA? Why would it imply that? Those are all z/OS software constructs or limitations, not anything to do with the hardware as far as I know. They're already possible with today's zArchitecture, if z/OS wanted to allow/implement them. Of course, the scrunched PSWs are also for application compatibility, so doig away with them would be a big change for everyone, not just z/OS. -- Walt ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
