sme...@gmu.edu (Seymour J Metz) writes: > On the S/360 the Alternate CPU Recovery facility was limited to 65MP > (I don't know about 9020 or TSS/360.) On MVS it was a standard > facility, although on an AP or MP without Channel Set Switching losing > the processor with the I/O channels was fatal. With MVS/XA and later > I/O was more robust.
360/65MP shared memory ... but processors had their own dedicated channels, to simulate "shared" i/o, it required controllers with multi-channel interfaces. 360/67MP had "channel controller" ... that included all channels to be accessed by all processors .... had bunch of switches to reconfigure hardware ... and switch settings were visible in the control registers. It also had hardware multiple paths to memory, introduced additional latency overhead ... but for I/O intensive workloads (where processors and I/O could simultaneously be doing transfers) it could have significant higher throughput (non-MP 360/67 was more like 65 and other 360s, where I/O memory accesses could interfer with cpu memory accesses). Could order a MP with only one processor and get channel controller and independent paths to memory. http://www.bitsavers.org/pdf/ibm/360/funcChar/A27-2719-0_360-67_funcChar.pdf Originally 360/67 announcement was for up to four processors (and the channel controller control register values had fields for all four processors). However (mostly) just two processors were built ... except for a special three processor 360/67 done for Lockheed and the manned orbital laboratory project. https://en.wikipedia.org/wiki/Manned_Orbiting_Laboratory tri-plex machine also provided for the configuration switch settings to be changed by changing the control register values (not just sensing the switch settings). -- virtualization experience starting Jan1968, online at home since Mar1970 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
