On Tue, 5 Apr 2011 10:19:16 +1000, Dave Airlie <[email protected]> wrote: > On Tue, Apr 5, 2011 at 2:26 AM, Keith Packard <[email protected]> wrote: > > On Mon, 04 Apr 2011 16:29:55 +0100, Chris Wilson <[email protected]> > > wrote: > > > >> Yes. I'm saying that that the controller accepts a write to port 0xa0. > > > > So it's the GMBUS controller itself then, I guess. Weird. > > > > Let me see if I understand how it used to work and why fixing the GMBUS > > reset causes it to break in this case. > > > > I could be missing something here, but aren't i2c addresses 8-bit in this > case? > > 7-bit addr + direction bit, which means 0xa0 isn't valid i2c address, > since in Linux > the read/write bits are specified separately.
Could this be is a mis-translation of some X server code? The X server stuck the direction bit in the LSB of the I2C address and required that the drivers shift the register up and add the direction bit manually (yes, a terrible API). This is starting to make a lot more sense now. 0xa0 == 0x50 << 1. -- [email protected]
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