Add a per ring lookup table, and #defines to clarify semaphore waits. Rename ring variables in sync function to clearly show correct names based on canonical semaphore naming.
Cc: Daniel Vetter <[email protected]> Signed-off-by: Ben Widawsky <[email protected]> --- drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++++++ drivers/gpu/drm/i915/intel_ringbuffer.c | 28 +++++++++++++++++++--------- drivers/gpu/drm/i915/intel_ringbuffer.h | 2 ++ 3 files changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f1cc55a..fd087b6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -189,11 +189,26 @@ #define MI_BATCH_NON_SECURE (1) #define MI_BATCH_NON_SECURE_I965 (1<<8) #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) + +/* Semaphore mailboxes are a bit tricky to understand based on names. + * There are NUM_RINGS-1 mailboxes per ring, and they are written to by + * the other ring(s). When a ring wishes to wait, it does so by + * comparing the value in it's own mailbox register, and SW must program + * which mailbox to compare against. + */ #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) #define MI_SEMAPHORE_UPDATE (1<<21) #define MI_SEMAPHORE_COMPARE (1<<20) #define MI_SEMAPHORE_REGISTER (1<<18) +#define MI_SEMAPHORE_SYNC_RV (2<<16) +#define MI_SEMAPHORE_SYNC_RB (0<<16) +#define MI_SEMAPHORE_SYNC_VR (0<<16) +#define MI_SEMAPHORE_SYNC_VB (2<<16) +#define MI_SEMAPHORE_SYNC_BR (2<<16) +#define MI_SEMAPHORE_SYNC_BV (0<<16) +#define MI_SEMAPHORE_SYNC_INVALID (1<<0) + /* * 3D instructions used by the kernel */ diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 9be0f11..2aac49e 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -359,25 +359,25 @@ gen6_add_request(struct intel_ring_buffer *ring, } int -intel_ring_sync(struct intel_ring_buffer *ring, - struct intel_ring_buffer *to, +intel_ring_sync(struct intel_ring_buffer *waiter, + struct intel_ring_buffer *signaller, u32 seqno) { int ret; - ret = intel_ring_begin(ring, 4); + ret = intel_ring_begin(waiter, 4); if (ret) return ret; - intel_ring_emit(ring, + intel_ring_emit(waiter, MI_SEMAPHORE_MBOX | MI_SEMAPHORE_REGISTER | - intel_ring_sync_index(ring, to) << 17 | + signaller->semaphore_register[waiter->id] | MI_SEMAPHORE_COMPARE); - intel_ring_emit(ring, seqno); - intel_ring_emit(ring, 0); - intel_ring_emit(ring, MI_NOOP); - intel_ring_advance(ring); + intel_ring_emit(waiter, seqno); + intel_ring_emit(waiter, 0); + intel_ring_emit(waiter, MI_NOOP); + intel_ring_advance(waiter); return 0; } @@ -1021,6 +1021,10 @@ static const struct intel_ring_buffer render_ring = { .irq_put = render_ring_put_irq, .dispatch_execbuffer = render_ring_dispatch_execbuffer, .cleanup = render_ring_cleanup, + .semaphore_register = {MI_SEMAPHORE_SYNC_INVALID, + MI_SEMAPHORE_SYNC_RV, + MI_SEMAPHORE_SYNC_RB}, + }; /* ring buffer for bit-stream decoder */ @@ -1148,6 +1152,9 @@ static const struct intel_ring_buffer gen6_bsd_ring = { .irq_get = gen6_bsd_ring_get_irq, .irq_put = gen6_bsd_ring_put_irq, .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, + .semaphore_register = {MI_SEMAPHORE_SYNC_VR, + MI_SEMAPHORE_SYNC_INVALID, + MI_SEMAPHORE_SYNC_VB}, }; /* Blitter support (SandyBridge+) */ @@ -1279,6 +1286,9 @@ static const struct intel_ring_buffer gen6_blt_ring = { .irq_put = blt_ring_put_irq, .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, .cleanup = blt_ring_cleanup, + .semaphore_register = {MI_SEMAPHORE_SYNC_BR, + MI_SEMAPHORE_SYNC_BV, + MI_SEMAPHORE_SYNC_INVALID}, }; int intel_init_render_ring_buffer(struct drm_device *dev) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 0029978..13167c6 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -72,6 +72,8 @@ struct intel_ring_buffer { u32 offset, u32 length); void (*cleanup)(struct intel_ring_buffer *ring); + u32 semaphore_register[3]; /*our mbox written by others */ + /** * List of objects currently involved in rendering from the * ringbuffer. -- 1.7.6.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
