As we defer updating the fence register from set-tiling to the point of use, we need to declare every access through the GTT as either fenced or unfenced.
This patches fixes up a couple of freshly introduced GTT accesses which missed the fence flush. Signed-off-by: Chris Wilson <[email protected]> --- drivers/gpu/drm/i915/i915_gem.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index a6819c1..19ca320 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -400,6 +400,10 @@ i915_gem_shmem_pread(struct drm_device *dev, ret = i915_gem_object_set_to_gtt_domain(obj, false); if (ret) return ret; + + ret = i915_gem_object_put_fence(obj); + if (ret) + return ret; } offset = args->offset; @@ -717,6 +721,10 @@ i915_gem_shmem_pwrite(struct drm_device *dev, ret = i915_gem_object_set_to_gtt_domain(obj, true); if (ret) return ret; + + ret = i915_gem_object_put_fence(obj); + if (ret) + return ret; } /* Same trick applies for invalidate partially written cachelines before * writing. */ -- 1.7.10 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
