Quoting Ville Syrjala (2017-11-08 13:35:55)
> From: Ville Syrjälä <[email protected]>
> 
> Apparently setting up a bunch of GT registers before we've properly
> initialized the rest of the GT hardware leads to these setting being
> lost. So looks like I broke HSW with commit b7048ea12fbb ("drm/i915:
> Do .init_clock_gating() earlier to avoid it clobbering watermarks")
> by doing init_clock_gating() too early. This should actually affect
> other platforms as well, but apparently not to such a great degree.
> 
> What I was ultimately after in that commit was to move the
> ilk_init_lp_watermarks() call earlier. So let's undo the damage and
> move init_clock_gating() back to where it was, and call
> ilk_init_lp_watermarks() just before the watermark state readout.
> 
> This highlights how fragile and messed up our init order really is.
> I wonder why we even initialize the display before gem. The opposite
> order would make much more sense to me...
> 
> v2: Keep WaRsPkgCStateDisplayPMReq:hsw early as it really must
>     be done before all planes might get disabled.
> 
> Cc: [email protected]
> Cc: Chris Wilson <[email protected]>
> Cc: Mark Janes <[email protected]>
> Cc: Maarten Lankhorst <[email protected]>
> Cc: Daniel Vetter <[email protected]>
> Cc: Joonas Lahtinen <[email protected]>
> Cc: Oscar Mateo <[email protected]>
> Cc: Mika Kuoppala <[email protected]>
> Reported-by: Mark Janes <[email protected]>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103549
> Fixes: b7048ea12fbb ("drm/i915: Do .init_clock_gating() earlier to avoid it 
> clobbering watermarks")
> References: 
> https://lists.freedesktop.org/archives/intel-gfx/2017-November/145432.html
> Signed-off-by: Ville Syrjälä <[email protected]>

CTS remains fixed,
Tested-by: Chris Wilson <[email protected]>

I know of no reason why this should work in this order,
Reviewed-by: Chris Wilson <[email protected]>
(but I didn't know about the v2 requirement either!)
-Chris
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