Quoting Daniele Ceraolo Spurio (2018-03-12 23:47:48)
> The only usage outside the intel_lrc.c file is in the ringbuffer
> init, but the irq mask calculated there is then overwritten for
> all engines that have a non-zero shift, so we can drop it.
> 
> This change is not aimed at code saving but at removing from
> intel_engines information that does not apply to all gens that have
> the engine. When checking without the temporary WARN_ON, code size
> is basically unchanged.
> 
> v2: make the irq_shifts array static const
> v3: rebase, move irq_shifts array to logical_ring_default_irqs
> 
> Suggested-by: Michel Thierry <michel.thie...@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
> Cc: Chris Wilson <ch...@chris-wilson.co.uk>
> Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk> #v2
> ---
> index 5e8f6896d059..aa1587c213aa 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2118,7 +2118,19 @@ logical_ring_default_vfuncs(struct intel_engine_cs 
> *engine)
>  static inline void
>  logical_ring_default_irqs(struct intel_engine_cs *engine)
>  {
> -       unsigned shift = engine->irq_shift;
> +       /* irq shifts for gen 8-10 */

You can plonk the array inside the gen8-10 branch so you don't even need
the comment.

> +       const unsigned int irq_shifts[] = {
> +               [RCS] = GEN8_RCS_IRQ_SHIFT,
> +               [BCS] = GEN8_BCS_IRQ_SHIFT,
> +               [VCS] = GEN8_VCS1_IRQ_SHIFT,
> +               [VCS2] = GEN8_VCS2_IRQ_SHIFT,
> +               [VECS] = GEN8_VECS_IRQ_SHIFT,
> +       };

Make it u8.

Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk>

You'll need to resend as a new thread as patchwork doesn't handle a
series gaining patches gracefully.
-Chris
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