== Series Details == Series: Display Stream Compression enabling on eDP/DP (rev4) URL : https://patchwork.freedesktop.org/series/47514/ State : warning
== Summary == $ dim sparse origin/drm-tip Commit: drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming Okay! Commit: drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Okay! Commit: drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Okay! Commit: drm/dp: DRM DP helper/macros to get DP sink DSC parameters Okay! Commit: drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC +drivers/gpu/drm/i915/intel_dp.c:4126:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4126:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4169:27: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4169:27: warning: expression using sizeof(void) Commit: drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Okay! Commit: drm/dp: Define payload size for DP SDP PPS packet Okay! Commit: drm/dsc: Define Display Stream Compression PPS infoframe Okay! Commit: drm/dsc: Define VESA Display Stream Compression Capabilities Okay! Commit: drm/dsc: Define Rate Control values that do not change over configurations Okay! Commit: drm/dsc: Add helpers for DSC picture parameter set infoframes - +drivers/gpu/drm/drm_dsc.c:195:61: expected restricted __be16 <noident> +drivers/gpu/drm/drm_dsc.c:195:61: got unsigned short [unsigned] [usertype] <noident> +drivers/gpu/drm/drm_dsc.c:195:61: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/drm_dsc.c:202:25: expected unsigned short [unsigned] [usertype] val +drivers/gpu/drm/drm_dsc.c:202:25: got restricted __be16 <noident> +drivers/gpu/drm/drm_dsc.c:202:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:202:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:202:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:202:25: warning: incorrect type in argument 1 (different base types) Commit: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state -drivers/gpu/drm/i915/selftests/../i915_drv.h:3689:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3690:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Compute DSC pipe config in atomic check +drivers/gpu/drm/i915/intel_dp.c:1902:23: warning: expression using sizeof(void) Commit: drm/i915/dp: Do not enable PSR2 if DSC is enabled Okay! Commit: drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Okay! Commit: drm/i915/dsc: Define & Compute VESA DSC params +drivers/gpu/drm/i915/intel_vdsc.c:351:17: warning: expression using sizeof(void) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000000000000000 becomes 0) Commit: drm/i915/dsc: Compute Rate Control parameters for DSC Okay! Commit: drm/i915/dp: Enable/Disable DSC in DP Sink Okay! Commit: drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Okay! Commit: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling -drivers/gpu/drm/i915/selftests/../i915_drv.h:3690:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3692:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Okay! Commit: drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Okay! Commit: drm/i915/icl: Add Display Stream Splitter control registers Okay! Commit: drm/i915/dp: Configure Display stream splitter registers during DSC enable Okay! Commit: drm/i915/dp: Disable DSC in source by disabling DSS CTL bits -drivers/gpu/drm/i915/selftests/../i915_drv.h:3692:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3694:16: warning: expression using sizeof(void) _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
