On Mon, Feb 04, 2019 at 10:21:39PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä <[email protected]> > > We need configure PIPE_CHICKEN during fastboot as well. Let's extract > it to a helper. > > v2: Apparently PIPE_CHICKEN is icl+ only > > Signed-off-by: Ville Syrjälä <[email protected]>
Reviewed-by: Matt Roper <[email protected]> > --- > drivers/gpu/drm/i915/intel_display.c | 31 ++++++++++++++++++---------- > 1 file changed, 20 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index df7a7a310f2f..4087d54ea943 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -3896,6 +3896,24 @@ void intel_finish_reset(struct drm_i915_private > *dev_priv) > clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags); > } > > +static void icl_set_pipe_chicken(struct intel_crtc *crtc) > +{ > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > + enum pipe pipe = crtc->pipe; > + u32 tmp; > + > + tmp = I915_READ(PIPE_CHICKEN(pipe)); > + > + /* > + * Display WA #1153: icl > + * enable hardware to bypass the alpha math > + * and rounding for per-pixel values 00 and 0xff > + */ > + tmp |= PER_PIXEL_ALPHA_BYPASS_EN; > + > + I915_WRITE(PIPE_CHICKEN(pipe), tmp); > +} > + > static void intel_update_pipe_config(const struct intel_crtc_state > *old_crtc_state, > const struct intel_crtc_state > *new_crtc_state) > { > @@ -5782,7 +5800,6 @@ static void haswell_crtc_enable(struct intel_crtc_state > *pipe_config, > struct intel_atomic_state *old_intel_state = > to_intel_atomic_state(old_state); > bool psl_clkgate_wa; > - u32 pipe_chicken; > > if (WARN_ON(intel_crtc->active)) > return; > @@ -5839,16 +5856,8 @@ static void haswell_crtc_enable(struct > intel_crtc_state *pipe_config, > */ > intel_color_load_luts(pipe_config); > > - /* > - * Display WA #1153: enable hardware to bypass the alpha math > - * and rounding for per-pixel values 00 and 0xff > - */ > - if (INTEL_GEN(dev_priv) >= 11) { > - pipe_chicken = I915_READ(PIPE_CHICKEN(pipe)); > - if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN)) > - I915_WRITE_FW(PIPE_CHICKEN(pipe), > - pipe_chicken | PER_PIXEL_ALPHA_BYPASS_EN); > - } > + if (INTEL_GEN(dev_priv) >= 11) > + icl_set_pipe_chicken(intel_crtc); > > intel_ddi_set_pipe_settings(pipe_config); > if (!transcoder_is_dsi(cpu_transcoder)) > -- > 2.19.2 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer IoTG Platform Enabling & Development Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
