From: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
Enable FtrPerCtxtPreemptionGranularityControl bit and select thread-
group as the default preemption level.
v2:
* Remove register whitelisting (Rafael, Tony).
Signed-off-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
Cc: Michał Winiarski <michal.winiar...@intel.com>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: piotr.zdunow...@intel.com
Cc: michal.mro...@intel.com
Cc: Tony Ye <tony...@intel.com>
Cc: Rafael Antognolli <rafael.antogno...@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index cb7d85c42f13..7be71a1a5719 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -601,6 +601,11 @@ static void tgl_ctx_workarounds_init(struct
intel_engine_cs *engine,
*/
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
FF_MODE2_TDS_TIMER_128, 0);
+
+ /* WaDisableGPGPUMidThreadPreemption:tgl */
+ WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
+ GEN9_PREEMPT_GPGPU_LEVEL_MASK,
+ GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
}
static void
@@ -1475,8 +1480,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct
i915_wa_list *wal)
PSDUNIT_CLKGATE_DIS);
}
- if (IS_GEN_RANGE(i915, 9, 11)) {
- /*
FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl */
+ if (IS_GEN_RANGE(i915, 9, 12)) {
+ /*
FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
wa_masked_en(wal,
GEN7_FF_SLICE_CS_CHICKEN1,
GEN9_FFSC_PERCTX_PREEMPT_CTRL);
--
2.20.1
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