Quoting Mika Kuoppala (2020-04-21 14:16:29) > More often than not, we need a byte offset into lrc > register state from the start of the hw state. Make it so. > > Signed-off-by: Mika Kuoppala <[email protected]> Reviewed-by: Chris Wilson <[email protected]> -Chris _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
- Re: [Intel-gfx] [PATCH 5/5] drm/i915: Split ctx tim... Mika Kuoppala
- [Intel-gfx] [PATCH 5/5] drm/i915: Split ctx timesta... Mika Kuoppala
- Re: [Intel-gfx] [PATCH 5/5] drm/i915: Split ctx... Chris Wilson
- [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting ... Patchwork
- [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1... Patchwork
- [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting ... Patchwork
- [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1... Patchwork
- [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1... Patchwork
- [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting ... Patchwork
- [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1... Patchwork
- Re: [Intel-gfx] [PATCH 1/5] drm/i915: Make define for lrc st... Chris Wilson
- [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1... Patchwork
