> -----Original Message-----
> From: Intel-xe <intel-xe-boun...@lists.freedesktop.org> On Behalf Of Imre Deak
> Sent: Tuesday, 5 August 2025 10.37
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: sta...@vger.kernel.org; Lin, Charlton <charlton....@intel.com>;
> Almahallawy, Khaled <khaled.almahall...@intel.com>
> Subject: [PATCH 04/19] drm/i915/lnl+/tc: Use the cached max lane count value
>
> Use the cached max lane count value on LNL+, to account for scenarios where
> this value is queried after the HW cleared the
> corresponding pin assignment value in the TCSS_DDI_STATUS register after the
> sink got disconnected.
>
> For consistency, follow-up changes will use the cached max lane count value
> on other platforms as well and will also cache the pin
> assignment value in a similar way.
>
> Cc: sta...@vger.kernel.org # v6.8+
> Reported-by: Charlton Lin <charlton....@intel.com>
> Tested-by: Khaled Almahallawy <khaled.almahall...@intel.com>
Reviewed-by: Mika Kahola <mika.kah...@intel.com>
> Signed-off-by: Imre Deak <imre.d...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_tc.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> b/drivers/gpu/drm/i915/display/intel_tc.c
> index ea93893980e17..14042a64375e1 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -395,12 +395,16 @@ static void read_pin_configuration(struct intel_tc_port
> *tc)
>
> int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port) {
> + struct intel_display *display = to_intel_display(dig_port);
> struct intel_tc_port *tc = to_tc_port(dig_port);
>
> if (!intel_encoder_is_tc(&dig_port->base))
> return 4;
>
> - return get_max_lane_count(tc);
> + if (DISPLAY_VER(display) < 20)
> + return get_max_lane_count(tc);
> +
> + return tc->max_lane_count;
> }
>
> void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
> --
> 2.49.1
