From: Ville Syrjälä <[email protected]> Pause the DMC DC Balancing for the remainder of the commit so that vmin/vmax won't change after we've baked them into the DSB vblank evasion commands.
--v2: - Remove typo. (Ankit) - Separate vrr enable structuring. (Ankit) --v3: - Add gaurd before accessing DC balance bits. - Remove redundancy checks. Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Mitul Golani <[email protected]> Reviewed-by: Ankit Nautiyal <[email protected]> --- drivers/gpu/drm/i915/display/intel_display.c | 19 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vrr.c | 5 +++++ 2 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index faec325e7652..b88e20418327 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7335,6 +7335,21 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, if (new_crtc_state->use_flipq) intel_flipq_wait_dmc_halt(new_crtc_state->dsb_commit, crtc); + if (new_crtc_state->vrr.dc_balance.enable) { + /* + * Pause the DMC DC balancing for the remainder of + * the commit so that vmin/vmax won't change after + * we've baked them into the DSB vblank evasion + * commands. + * + * FIXME maybe need a small delay here to make sure + * DMC has finished updating the values? Or we need + * a better DMC<->driver protocol that gives is real + * guarantees about that... + */ + intel_pipedmc_dcb_disable(NULL, crtc); + } + if (intel_crtc_needs_color_update(new_crtc_state)) intel_color_commit_noarm(new_crtc_state->dsb_commit, new_crtc_state); @@ -7396,6 +7411,10 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, intel_vrr_check_push_sent(new_crtc_state->dsb_commit, new_crtc_state); + + if (new_crtc_state->vrr.dc_balance.enable) + intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc); + intel_dsb_interrupt(new_crtc_state->dsb_commit); } diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 97949ff782aa..eb6643ec5194 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -9,6 +9,7 @@ #include "intel_de.h" #include "intel_display_regs.h" #include "intel_display_types.h" +#include "intel_dmc.h" #include "intel_dmc_regs.h" #include "intel_dp.h" #include "intel_psr.h" @@ -813,6 +814,9 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state, if (cmrr_enable) vrr_ctl |= VRR_CTL_CMRR_ENABLE; + if (crtc_state->vrr.dc_balance.enable) + intel_pipedmc_dcb_enable(NULL, crtc); + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl); } @@ -834,6 +838,7 @@ static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state) intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); if (old_crtc_state->vrr.dc_balance.enable) { + intel_pipedmc_dcb_disable(NULL, crtc); intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0); intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0); intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 0); -- 2.48.1
