Re: [RESEND, 10/22] drm/i915/vrr: Add function to reset DC Balance flip count

[Nautiyal, Ankit K]

On 11/3/2025 10:59 AM, Mitul Golani wrote:
Reset DC balance flip count value while disabling VRR
adaptive mode, this is to start with fresh counts when
VRR adaptive refresh mode is triggered again.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com>
---
  drivers/gpu/drm/i915/display/intel_display.c |  1 +
  drivers/gpu/drm/i915/display/intel_vrr.c     | 12 ++++++++++++
  drivers/gpu/drm/i915/display/intel_vrr.h     |  2 ++
  3 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 1a3e7a6e4ab7..323293f4bf6d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1148,6 +1148,7 @@ static void intel_pre_plane_update(struct 
intel_atomic_state *state,
  
  	if (intel_crtc_vrr_disabling(state, crtc)) {
                intel_vrr_disable(old_crtc_state);
+               intel_vrr_dcb_reset_flip_count(old_crtc_state, crtc);


IMHO we should merge patches#8,9,10 to have a single patch that 
introduces a new member flip_count to struct intel_crtc, and to 
increment and reset the counter.


Regards,

Ankit


                intel_crtc_update_active_timings(old_crtc_state, false);
        }
  
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 87bd722aa32d..2ae27751e5b4 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -627,6 +627,18 @@ intel_vrr_dcb_increment_flip_count(struct intel_crtc_state 
*crtc_state,
                       ++crtc->dc_balance.flip_count);
  }
  
+void intel_vrr_dcb_reset_flip_count(const struct intel_crtc_state *crtc_state,
+                                   struct intel_crtc *crtc)
+{
+       struct intel_display *display = to_intel_display(crtc_state);
+       enum pipe pipe = crtc->pipe;
+
+       if (!crtc_state->vrr.dc_balance.enable)
+               return;
+
+       intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe), 0);
+}
+
  void intel_vrr_send_push(struct intel_dsb *dsb,
                         const struct intel_crtc_state *crtc_state)
  {
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h 
b/drivers/gpu/drm/i915/display/intel_vrr.h
index eebc7be309db..8f97525b8e2d 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -42,6 +42,8 @@ void intel_vrr_transcoder_disable(const struct 
intel_crtc_state *crtc_state);
  void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state 
*crtc_state);
  void intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state,
                                        struct intel_crtc *crtc);
+void intel_vrr_dcb_reset_flip_count(const struct intel_crtc_state *crtc_state,
+                                   struct intel_crtc *crtc);
  bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
  int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state);
  int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);